Methods for forming small-scale capacitor structures

ABSTRACT

The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a a divisional of U.S. application Ser. No.13/047,430 filed Mar. 14, 2011, now U.S. Pat. No. 8,384,192, which is adivisional of U.S. application Ser. No. 10/767,298 filed Jan. 28, 2004,now U.S. Pat. No. 7,906,393, each of which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

The present invention is related to methods for forming capacitors onmicrofeature workpieces, e.g., semiconductor substrates. Aspects of theinvention have particular utility in connection with forming capacitorsfor use in microelectronic components, e.g., DRAM capacitors.

BACKGROUND

Recent advances in the miniaturization of integrated circuits have ledto smaller chip areas available for devices. High density dynamic randomaccess memory chips (DRAMs), for example, leave little room for thestorage node of a memory cell. Yet, the storage node (capacitor) must beable to store a certain minimum charge, determined by design andoperational parameters, to ensure reliable operation of the memory cell.It is thus increasingly important that capacitors achieve a high storedcharge per unit of chip area occupied.

Traditionally, capacitors integrated into memory cells have structuresbased on the parallel plate capacitor. A layer of dielectric is disposedbetween two conductive layers and the layers are patterned, eithersequentially during deposition or all at once. The patterned dielectriclayer becomes the capacitor dielectric while the patterned conductivelayers become the top and bottom plates or electrodes of the resultantcapacitor structure. The charge stored on the capacitor is proportionalto the capacitance (C) of the capacitor, C=K K₀ A/d, where K is thedielectric constant of the capacitor dielectric, K₀ is the vacuumpermittivity, A is the electrode area, and d is the spacing betweenelectrodes.

Several techniques have been developed to increase the total chargecapacity of the cell capacitor without significantly affecting the chiparea occupied by the cell. These include increasing the effectivesurface area (A) of the electrodes by creating folding structures, suchas trench or stacked capacitors. Such structures better utilize theavailable chip area by creating three-dimensional shapes to which theconductive electrodes and interlayer dielectric conform.

One common way to increase the surface area of the capacitor electrodesemploys a roughened or texturized electrode surface. U.S. PatentApplication Publication 2003/0003697 to Agarwal et al. (the entirety ofwhich is incorporated by reference), for example, suggests a roughenedelectrode surface that may comprise annealed ruthenium oxide. Moreconventionally, roughened polycrystalline silicon (commonly referred toas “polysilicon,” or simply “poly”) in the form of hemispherical grainedpolysilicon (commonly referred to as “HSG silicon” or “HSG polysilicon”)has been used for a number of years as the bottom or storage electrodeof microelectronic capacitors. Such bottom electrodes are commonly incontact with an active area of a silicon substrate that comprises partof a transistor. A thin dielectric layer is formed atop the bottomelectrode and typically conforms reasonably well to the rough electrodesurface. A top electrode may be deposited on the dielectric layer. Theconformality of the dielectric layer commonly provides the outer surfaceof the dielectric layer with a roughened surface as well. The use of arough bottom electrode, e.g., a layer of HSG polysilicon, thuseffectively increases the electrode area (A in the capacitance formulaabove), which increases the capacitance of the capacitor structure.

As a bottom electrode for a capacitor, however, roughened polysilicon istypically doped for conductivity to allow the bottom electrode to holdthe requisite amount of charge. Unfortunately, rough polysilicondeposition techniques, such as HSG vacuum annealing, are most effectiveat lower doping levels. Further doping the polysilicon of the bottomelectrode tends to result in diffusion of the dopants through the bottomelectrode to the underlying active area of the substrate. For example,phosphorus from solid source P₂O₅, a commonly employed dopant, diffuseseasily through silicon during high temperature anneal steps. Downwardlydiffused dopants can interfere with junction operation by changing thedopant profile of the active area and the transistor characteristics.Although some implanted dopants, such as arsenic ions, tend to diffusemore slowly, they may fail to adequately dope vertical surfaces, areoften unduly expensive, and generally do not entirely eliminate thediffusion problem.

Some have proposed depositing an electrically conductive layer on top ofa HSG silicon bottom electrode. For example, U.S. Pat. No. 6,211,033,issued to Sandhu et al. (the entirety of which is incorporated herein byreference), suggests depositing a layer of titanium nitride or titaniumcarbonitride on the outer surface of an HSG silicon electrode. The useof such a conductive overcoat can lead to greater conductivity in thebottom electrode with less doping of the HSG silicon layer and decreaseddiffusion of dopants. Such a titanium nitride or titanium carbonitridelayer can also serve as an interface for high-stress locations in theHSG silicon layer, reducing the risk of cracking of the dielectric layerand the resultant current leakage. This Sandhu et al. patent suggestsforming the titanium nitride or titanium carbonitride layer by metalorganic chemical vapor deposition (MOCVD) employingtetrakis(dimethylamido)titanium (TDMAT) and a nitrogen carrier gas, orby CVD with a titanium halide, e.g., TiCl₄, as the titanium source andammonia as the nitrogen source. Both of these CVD techniques canintroduce significant levels of impurities in the resultant titaniumnitride or titanium carbonitride film. Using MOCVD can incorporatecarbon as an impurity in the form of titanium carbide. If the titaniumnitride layer is instead deposited using titanium chloride and ammonia,chlorine atoms from the TiCl₄ can be incorporated in the depositedmaterial and diffuse into the silicon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of a system including a reactor fordepositing a material on a single microfeature workpiece in accordancewith select embodiments of the invention.

FIG. 2 is a schematic representation of a system including a reactor fordepositing a material on surfaces of multiple microfeature workpieces inaccordance with other embodiments of the invention.

FIG. 3 is a schematic illustration of one exemplary process for formingan electrically conductive layer in accordance with one aspect of theinvention.

FIG. 4 is a schematic illustration of one exemplary process for forminganother electrically conductive layer in accordance with another aspectof the invention.

FIG. 5 is a schematic illustration of an alternative process for formingan electrically conductive layer in accordance with still another aspectof the invention.

FIG. 6 schematically illustrates a first stage in the formation of amicroelectronic capacitor in accordance with one embodiment of theinvention.

FIG. 7 schematically illustrates the structure of FIG. 5 and asubsequent stage of manufacture.

FIG. 8A is a schematic illustration of the structure of FIG. 6 afteraddition of a first electrically conductive layer.

FIG. 8B is an enlarged close up view of the encircled area of FIG. 7A.

FIG. 9A is a schematic illustration of the device of FIG. 7A bearinganother electrically conductive layer.

FIG. 9B is an enlarged isolation view of the encircled portion of FIG.8A.

FIG. 9C is an enlarged isolation view, similar to FIG. 9B, of a portionof a device in accordance with another embodiment of the invention.

FIG. 9D is an enlarged isolation view, similar to FIG. 9B, of a portionof a device in accordance with an alternative embodiment of theinvention.

FIG. 10 is a schematic illustration of the device of FIG. 6A bearing adielectric layer.

FIG. 11 is a schematic illustration of the device of FIG. 9 afteraddition of a second electrode layer.

FIG. 12 is a schematic illustration of a microelectronic capacitor inaccordance with one particular embodiment of the invention.

FIG. 13 is a schematic illustration of a microelectronic capacitor inaccordance with another embodiment of the invention.

FIG. 14 is a schematic illustration of a microelectronic capacitor inaccordance with still another embodiment of the invention.

DETAILED DESCRIPTION A. Overview

Various embodiments of the present invention provide methods of formingcapacitors, e.g., capacitors employed as features of microelectroniccomponents. Other embodiments of the invention provide microelectroniccomponents that include capacitors. The term “microfeature workpiece” isused throughout to include substrates upon which and/or in whichmicroelectronic devices, micromechanical devices, data storage elements,read/write components, and other features are fabricated. For example,microfeature workpieces can be semiconductor wafers such as silicon orgallium arsenide wafers, glass substrates such as borophosphosilicateglass (BPSG), and other types of materials. The microfeature workpiecestypically have submicron features with dimensions of 0.05 microns orgreater. Furthermore, the terms “gas” and “gaseous” are used throughoutto include any form of matter that has no fixed shape and will conformin volume to the space available, which specifically includes vapors(i.e., a gas having a temperature less than the critical temperature sothat it may be liquefied or solidified by compression at a constanttemperature).

Several embodiments in accordance with the invention are set forth inFIGS. 1-14 and the following text to provide a thorough understanding ofparticular embodiments of the invention. A person skilled in the artwill understand, however, that the invention may have additionalembodiments, or that the invention may be practiced without several ofthe details of the embodiments shown in FIGS. 1-14.

One embodiment of the invention provides a method of fabricating acapacitor that includes forming a first electrode on a surface of amicrofeature workpiece, forming a dielectric layer on the firstelectrode, and forming a second electrode over the dielectric layer. Atleast one of the first and second electrodes is formed by a) reacting afirst gaseous precursor and a second gaseous precursor to deposit afirst electrically conductive layer at a first deposition rate, and b)depositing a second electrically conductive layer at a second depositionrate that is less than the first deposition rate by depositing aprecursor layer of a third gaseous precursor (which may be the same asthe first precursor) at least one monolayer thick and exposing theprecursor layer to a fourth gaseous precursor (which may be the same asthe second precursor) to form a nanolayer reaction product. The secondelectrically conductive layer is in contact with the dielectric layerand may have a thickness of no greater than about 50 Å.

A method of fabricating a microelectronic capacitor in accordance withanother embodiment of the invention includes depositing first and secondconductive layers and, thereafter, depositing a dielectric layer anddepositing an electrode on the dielectric layer. The first conductivelayer is deposited at a first rate by reacting a first gaseous precursorand a second gaseous precursor in a first reaction process. The firstconductive layer has a first surface roughness and a first impuritycontent. The second conductive layer is deposited at a second rate,which is slower than the first rate, by reacting the first gaseousprecursor and the second gaseous precursor in a second reaction process.The second conductive layer has a second surface roughness that issmoother than the first surface roughness and a second impurity contentthat is lower than the first impurity content.

A method of fabricating a microelectronic capacitor in accordance withanother embodiment of the invention includes positioning a microfeatureworkpiece in a process chamber and forming an electrically conductivestructure on a surface of the microfeature workpiece. This surface maycomprise a patterned layer of the microfeature workpiece or the surfaceof a previously-deposited layer or coating. This electrically conductivestructure may be formed by sequentially depositing first, second, third,and fourth electrically conductive layers. The first electricallyconductive layer is deposited by a first deposition process thatcomprises contemporaneously introducing a first gaseous precursor and asecond gaseous precursor to the process chamber to form a first reactionproduct. The second electrically conductive layer is deposited on thefirst electrically conductive layer by a second deposition process. Thissecond deposition process may comprise alternately introducingquantities of the first and second precursors to the process chamber toform at least two layers of a second reaction product. The thirdelectrically conductive layer may be deposited on the secondelectrically conductive layer by the first deposition process outlinedabove, and the fourth electrically conductive layer may be deposited onthe third electrically conductive layer by the second deposition processoutlined above.

Yet another embodiment of the invention provides a microelectroniccomponent comprising a plurality of memory cells carried by a substrate.Each memory cell includes a capacitor that comprises a first electrode,a dielectric layer and a second electrode deposited on the dielectriclayer. The first electrode includes, moving outwardly from a surface ofthe substrate, a hemispherical grain polycrystalline silicon layer, alayer of a bulk deposition product comprising a primary species, and alayer of a nanolayer deposition product comprising the same primaryspecies. The layer of the nanolayer deposition product has a thicknessof no greater than 50A and the bulk deposition product has an impuritycontent higher than an impurity content of the nanolayer depositionproduct. The dielectric layer is deposited on the nanolayer depositionproduct of the first electrode.

For ease of understanding, the following discussion is subdivided intotwo areas of emphasis. The first section discusses aspects of processingsystems that may be used in accordance with selected embodiments of theinvention. The second section outlines methods in accordance with otheraspects of the invention.

B. Processing Systems

FIG. 1 schematically illustrates a reactor 10 that may be used to formcapacitors in accordance with select embodiments of the invention. Thereactor 10 of FIG. 1 includes a process chamber 20 coupled to a gassupply 30 and a vacuum 40. The reactor 10 may also include a heaterplate 50 that supports the microfeature workpiece W and a gas dispenser60, both of which are disposed in the process chamber 20. The gasdispenser 60 includes a plenum 62 operatively coupled to the gas supply30 and a distributor plate 70 having a plurality of holes 72. Inoperation, the heater plate 50 may heat the workpiece W to a desiredreaction temperature and the desired combination or series of gases maybe injected into the process chamber 20 via the gas dispenser 60. Thevacuum 40 can maintain a negative pressure in the process chamber 20 todraw the gases from the gas dispenser 60 across the workpiece W and thenthrough an outlet in the process chamber 20.

The gas supply 30 of the reactor 10 shown in FIG. 1 includes a pluralityof gas sources 31 (identified individually as 31 a-c), a valve assembly34 having a plurality of valves, and a plurality of gas supply lines 32and 36. The gas sources 31 can include any number of gases anticipatedto be needed for various reactions in the process chamber 20. In theparticular embodiment shown schematically in FIG. 1, the gas sources 31include a first gas source 31 a for providing a first gas, a second gassource 31 b for providing a second gas, and a third gas source 31 c forproviding a third gas. In one example, the first and second gases can befirst and second precursors, respectively, and the third gas can be apurge gas. As discussed in more detail below, the first and secondprecursors may be chemical species that react to form a reaction producton a surface of the microfeature workpiece W. The gas supply 30 caninclude more gas sources 31 for other applications that requireadditional precursors or purge gases. For example, the first and secondprecursors may be used to deposit an electrically conductive layer orlayers and an additional precursor or precursors may be provided inadditional gas sources 31 (not shown) to deposit a dielectric layer asdescribed below.

The valve assembly 34 may be operated by a controller 38 that generatessignals for controlling the flow of gases to the reaction chamber 20. Inone embodiment, this controller 38 comprises a computer having aprogrammable processor programmed to control operation of the valveassembly 34 to deposit material on the workpiece W. If so desired, thecontroller 38 may also be coupled to the vacuum 40 and/or the heater 50to further control the reaction conditions adjacent the surface of theworkpiece W. For example, the controller 38 can be programmed to heatthe workpiece to a desired temperature via the heater 50 and operate thevalve assembly 34 to pulse quantities of different gases individuallythrough the gas distributor 60 in atomic layer deposition (ALD)applications or mix selected precursors in the plenum 62 of the gasdistributor 60 in continuous or pulsed CVD processes.

The reactor 10 of FIG. 1 is adapted to receive and process a singlemicrofeature workpiece W in the process chamber 20. To increasethroughput of CVD and ALD processes, the microelectronics industry, forexample, is moving toward batch processing of workpieces W. FIG. 2schematically illustrates a reactor 12 adapted for batch processing ofworkpieces W. Many of the elements of this batch reactor 12 are similarto the reactor 10 of FIG. 1 and like reference numbers are used todesignate similar elements. In the embodiment of FIG. 1, the workpiece Wis supported on a heater plate 50 that is also adapted to heat theworkpiece W. In the batch reactor 12, one or more workpieces W may besupported in the process chamber 20 by a workpiece holder 52. Forexample, the workpiece holder 52 may be adapted to hold anywhere from 20to 250 microfeature workpieces W for concurrent processing. Themicrofeature workpieces W may be heated during processing by one or moreradiant heat panels 50 arranged about the periphery of the processchamber 20.

C. Methods of Depositing Materials on Micro-Device Workpieces

As noted above, other embodiments of the invention provide methods offorming capacitors, e.g., by forming a capacitor on a microfeatureworkpiece for use as a microelectronic capacitor. In the followingdiscussion, reference is made to the processing system 10 shownschematically in FIG. 1. It should be understood, though, that referenceto this particular processing system is solely for purposes ofillustration and that the methods outlined below are not limited to anyparticular processing system.

Deposition Techniques

As discussed below, various embodiments of the invention employ bothchemical vapor deposition (CVD) and atomic layer deposition (ALD). BothCVD and ALD, as used herein, involve the use of at least one chemicalspecies that can decompose or can react with another chemical species toform a desired material on the workpiece W. Such chemical species arereferred to herein as “precursors.” One of the differences between a CVDprocess employing two or more precursors and an ALD precursor employingtwo or more precursors is the relative timing of the delivery of theprecursors to the proximity of the workpiece W. In CVD processes, bothof the precursors are simultaneously present in and react in a spaceadjacent the surface of the workpiece W; in conventional ALD processes,the precursors are introduced separately and primarily react directly onthe surface of the workpiece W.

CVD is commonly used to deposit a completed reaction product on asurface of a workpiece W. The conditions adjacent a workpiece surfacemay be used to catalyze a gas-phase reaction or decomposition of theprecursor(s) to form a reaction product. This completed reaction productis deposited on the surface of the workpiece W. Commonly, both of theprecursors in a two-precursor CVD process are introducedcontemporaneously, i.e., during an overlapping period of time.

FIG. 3 schematically illustrates a gas flow of a CVD process 100 inaccordance with one embodiment of the invention as a plot of flow rateover time. In this process 100, a first gaseous precursor flow 101 and asecond gaseous precursor flow 102 are contemporaneously delivered to theprocess chamber 20 of the reactor 10. This may be accomplished bycontrolling the valve assembly 34 to deliver the first precursor fromthe first gas source 31 a and the second precursor from the second gassource 31 b. Both of these gases are delivered to the plenum 62 of thegas dispenser 60, where they will at least begin to be mixed together.This mixture of gases can then be delivered to the proximity of theworkpiece W by the distributor plate 70. In FIG. 3, the first gas flow101 and the second gas flow 102 are shown as starting and ending atsubstantially the same time. In other embodiments, the first gas flow101 may start before or after the second gas flow 102 is initiated andthe first gas flow 101 may be terminated before or after the second gasflow 102 is terminated. In each of these cases, the first gas flow 101and the second gas flow 102 may be said to be contemporaneous if theyoccur simultaneously over a material period of time, i.e., they need notstart and/or stop at the same time.

FIG. 3 schematically illustrates delivery of a purge/carrier gas. Inthis embodiment, the purge gas may be delivered before initiating thefirst and second gas flows 101 and 102 and again delivered to theprocess chamber 20 after the first and second gas flows 101 and 102 areterminated. Such a purge gas flow 103 may be used in conjunction withthe vacuum 40 to purge any excess precursors from the process chamber20. In other embodiments, the purge/carrier gas may be deliveredcontemporaneously with the first and second gaseous precursors, in whichcase it serves as a more conventional carrier gas to provide adequategas flow through the dispenser 60 while controlling the concentration ofthe precursors in the gas flow. In the context of FIG. 1, the third gasflow 103 may be delivered by selectively controlling the valve assembly34 to deliver the purge gas from the third gas source 31 c to the gasdispenser 60.

Atomic layer deposition, in contrast with CVD, generally involvesdelivering precursors in alternating pulses rather than delivering themcontemporaneously. FIG. 4 is a schematic plot of gas flow rates as afunction of time in accordance with an ALD process 110 in accordancewith one embodiment of the invention. In this process 110, discretequantities of the first gaseous precursor are delivered in firstprecursor pulses 111 a and 111 b. Discrete quantities of the secondgaseous precursor are delivered to the process chamber 20 in secondprecursor pulses 112 a and 112 b. The first pulses 111 and second pulses112 are delivered at different times in an alternating fashion.

Moving down the timeline of FIG. 4, one pulse 111 a of the firstprecursor may be delivered to the process chamber 20 to contact thesurface of the workpiece W. The precursor may be at least chemisorbed onthe workpiece W. Theoretically, such chemisorbtion will form a monolayerthat is uniformly one molecule thick on the entire surface of theworkpiece W. Such a monolayer may be referred to as a saturatedmonolayer. As a practical matter, in some circumstances some minorportions of the workpiece surface may not chemisorb a molecule of theprecursor. Nevertheless, such imperfect monolayers are still referred toherein as monolayers. In many applications, a substantially saturatedmonolayer may be suitable. A substantially saturated monolayer is amonolayer that will yield a deposited layer exhibiting the requisitequality and/or electrical properties.

An excess of the first precursor is typically delivered to the processchamber 20. This excess first precursor can be purged from the vicinityof the workpiece surface. Purging may involve a variety of techniques,including any combination of contacting the substrate and/or monolayerwith a purge gas and/or lowering pressure in the process chamber 20 tobelow the pressure needed to deposit the precursor on the workpiecesurface. Examples of suitable carrier gases include nitrogen, argon,helium, neon, krypton, and xenon. In the particular embodiment shown inFIG. 4, a first pulse 113 a of the purge gas is delivered to the processchamber 20 and a majority or all of this purge gas pulse 113 a may takeplace after the first precursor pulse 111 a is completed. The purgeprocess shown in FIG. 4 also includes a pump-down step 115 a wherein thevacuum 40 will withdraw gas from the process chamber 20 withoutintroducing any additional gas from the gas supply 30. The parameters ofthe purge pulse 113 a and pump-down 115 a may be determinedexperimentally, as known in the art. The pump-down time and/or thequantity of purge gas in the pulse 113 a may be successively reduceduntil the film growth rate increases. Such an increase in film growthrate may be deemed an indication that excess quantities of the firstprecursor remain in the process chamber 20, which may be used toestablish a minimum purge gas quantity and/or purge time.

Once the process chamber 20 has been suitably purged, a pulse 112 a ofthe second gaseous precursor may be delivered to the process chamber 20.This second precursor may chemisorb on the first monolayer of the firstprecursor and/or react with the monolayer to form a reaction product.This reaction product is typically one or no more than a few moleculesthick, yielding a very thin, highly conformal nanolayer reactionproduct. After a suitable exposure to the second gaseous precursor, thesecond precursor pulse 112 a may be terminated and the process chamber20 may be purged again with a pulse 113 b of purge gas and/or apump-down step 115 b.

As suggested in FIG. 4, the pair of precursor pulses 111 a and 112 a,together with the associated pulses 113 a and 113 b of purge gas and/orpump-down steps 115 a and 115 b, may be considered one cycle. This cyclewill form a nanolayer that is usually thinner than the desired totalthickness, with typical thicknesses of just 1 or 2 molecules (e.g., lessthan 1 nm, often less than 2 Å). As a consequence, the cycle is oftenrepeated numerous times to yield a layer with an appropriate thickness.Hence, FIG. 4 illustrates a second cycle that involves delivering afurther pulse 111 b of the first precursor, purging the process chamber20 with a further purge gas pulse 113 c and pump-down 115 c,subsequently delivering another second precursor pulse 112 b, and againpurging the process chamber 20 with another purge gas pulse 113d andpump-down 115 d. This process can be repeated as many times as necessaryto yield a layer of the desired thickness.

FIG. 5 schematically illustrates a gas flow profile analogous to FIG. 4,but illustrating a process 120 in accordance with another embodiment ofthe invention. In this process 120, pulses 121 a-d of the first gaseousprecursor are alternated with pulses 122 a-d of the second gaseousprecursor. This is similar in some respects to the pulses 111 and 112illustrated in FIG. 4 in the process 120 shown in FIG. 5. However, thereis no purge process (e.g., purge pulse 113 a and pump-down 115 a in FIG.4) between delivery of successive quantities of the first and secondprecursors. Hence, in FIG. 5, the first pulse 122 a of the secondgaseous precursor may immediately follow completion of the first pulse121 a of the first gaseous precursor. Likewise, the next pulse 121 b ofthe first precursor may immediately follow termination of the firstpulse 122 a of the second precursor. In this process, a monolayer of thefirst precursor may be deposited on the surface of the workpiece priorto delivery of the pulse of the second precursor. Without the purgephase, though, some of the first precursor may remain in the vicinity ofthe workpiece W when the next pulse of the second gaseous precursor isinitiated. This may result in a gaseous phase reaction between theprecursors in a gaseous, unbound phase, leading to direct deposition ofthe reaction product on the surface of the workpiece W, and an increasein the rate of film formation. By appropriately selecting the processconditions and the timing of the pulses 121 and 122, though, thisCVD-like secondary deposition may be held in check and may notsignificantly adversely affect the quality of the ALD-depositedmaterial.

In other embodiments, the process chamber 20 may be purged between some,but not all, precursor pulses. For example, one pulse (e.g., 121 a) ofthe first precursor and one pulse (e.g., 122 a) of the second precursormay form one cycle of material deposition. A purge step, which maycomprise delivery of a purge gas and/or a pump-down of the processchamber 20, may be performed between cycles to better promote depositionof a monolayer of the first precursor on the layer of material depositedin the previous cycle.

The process 120 shown in FIG. 5 may not technically conform toconventional definitions of atomic layer deposition because remnants ofone precursor are present when the subsequent precursor is introduced.Nonetheless, it is anticipated that such a “pseudo-ALD” process maydeliver many of the benefits desired from ALD layers in accordance withselect methods outlined below. As a consequence, the term “ALD” is usedherein to refer to both conventional ALD, (e.g., deposition via theprocess 110 illustrated in FIG. 3) and “pseudo-ALD” (e.g., depositionvia the process 120 shown in FIG. 4).

Under most CVD conditions, the reaction between the precursors occurslargely independently of the composition or surface properties of theworkpiece on which the reactant is being deposited. By contrast, thechemisorbtion rate of a precursor in ALD may be influenced by thecomposition, crystalline structure, and other properties of theworkpiece surface, including any previously chemisorbed chemical specieson that surface. If necessary, the surface of the workpiece can beprepared before ALD to enhance the deposition of the monolayer of thefirst precursor. For example, if an ALD layer is to be formed on HSGsilicon, it may be advantageous to expose the HSG silicon to water vaporto provide —OH termination at the surface.

ALD and CVD processes each have some advantages and disadvantages. Theprimary advantage of CVD in the context of the present invention is thatit may deposit material at a significantly higher rate than ALDprocesses. Whereas CVD techniques may require only about one minute toform a 60 Å thick layer, for example, ALD techniques using analogousprecursors may take several minutes to form a layer having the samethickness by depositing a series of nanolayers. In single-waferprocessing chambers, ALD processes can take 500-2000 percent longer thancorresponding single-wafer CVD processes.

Although ALD may take appreciably longer than CVD, materials depositedvia ALD are often superior in a number of respects to analogousmaterials deposited via CVD. For example, building up a layer of ALDmaterial as a series of independently deposited nanolayers can yieldsignificantly higher conformality to underlying surface roughness thanis typically achieved using CVD with the same precursors. Layersdeposited via CVD also tend to include a significantly higherconcentration of impurities than an analogous material deposited viaALD. As noted above in connection with U.S. Pat. No. 6,211,033,depositing titanium nitride or titanium carbonitride via MOCVD (e.g.,TDMAT/nitrogen) or CVD (e.g., TiCl₄/NH₃) can incorporate undesirableamounts of carbon and/or chlorine in the resultant layer. Thecrystallinity and crystal habit of the layer deposited via CVD will varydepending on the process conditions, but the grain size in crystallineCVD films is often larger than any grains that may develop in ALD films.This tends to produce a rougher surface on CVD-deposited layers than onanalogous ALD-deposited layers. Particularly if the dielectric is notdeposited in a highly conformal deposition process, this microroughnessof CVD layers may adversely impact the quality of the electricalinterface between a CVD-deposited electrode and an overlying dielectriclayer.

Manufacturing Processes

FIGS. 6-11 schematically illustrate sequential stages in the manufactureof a microelectronic capacitor 200 in accordance with one embodiment ofthe invention. Turning first to FIG. 6, the workpiece W shown in thisdrawing includes a semiconductor substrate 202 having a heavily dopedactive area 208. An electrically insulating layer 204 is carried by thesubstrate 202 and has an opening 206 that extends from an exterior ofthe insulating layer 204 down to the active area 208 of the substrate202. This provides the workpiece W with a three-dimensional outersurface S upon which materials will be deposited in subsequent steps. Aworkpiece W such as that shown in FIG. 6 may be made easily usingconventional techniques known in the art.

In FIG. 7, a hemispherical grain polysilicon layer 210 has been formedon the surface S of the workpiece W of FIG. 6. The HSG silicon layer 210has a rough surface 212 that increases the surface area of the layer, asdiscussed above. As discussed below, this HSG silicon layer 210 maydefine a layer of a bottom electrode of the capacitor 200. If sodesired, the HSG silicon layer 210 may be doped, e.g., with arsenic orphosphorous, to enhance its electrical conductivity. The HSG siliconlayer 210 may be formed in any of a variety of commonly known methods.One such method includes vacuum annealing of an amorphous silicon layeror a polysilicon layer with relatively small grain size, inducing graingrowth at nucleation sites. Another common method of forming HSG siliconincludes direct deposition, wherein polysilicon selectively grows atnucleation sites during deposition.

FIGS. 8A and 8B schematically illustrate the workpiece W of FIG. 7 afterdeposition of an electrically conductive CVD layer 220 on the roughsurface 212 of the HSG silicon layer 210. The CVD layer 220 may bedeposited in any of a variety of CVD processes that will yield anelectrically conductive layer 220 that conforms reasonably well to theroughened surface 212 of the HSG polysilicon. In certain embodiments ofthe invention, the CVD layer 220 is deposited by introducing a firstgaseous precursor and a second gaseous precursor to the process chamber20 of the reactor 10 at the same time so these gases may react and bedeposited directly on the surface 212 of the HSG layer 210. In oneexemplary embodiment, the CVD layer 220 comprises a layer of titaniumnitride formed by reaction of a titanium-containing first precursor anda nitrogen-containing second precursor. For example, a titanium nitrideCVD layer 220 may be deposited by introducing titanium chloride TiCl₄and NH₃ to the process chamber 20 under appropriate conditions, whichare widely known. In another embodiment employing MOCVD, TDMAT is usedas a metal organic precursor and nitrogen is used as a carrier gas. Assuggested in FIG. 8B, the outer surface 222 of the CVD layer 220, i.e.,the surface of the CVD layer 220 spaced away from the underlying HSGsilicon layer 210, may exhibit microroughness, illustrated schematicallyin FIG. 8B as an irregular outer surface 222.

As illustrated in FIGS. 9A and 9B, an ALD layer 230 may be deposited onthe outer surface 222 of the CVD layer 220. This ALD layer may be formedusing any suitable ALD technique, including, but not limited to, the ALDprocesses 110 and 120 shown in FIGS. 4 and 5, respectively. This ALDlayer 230 will typically comprise at least two nanolayers, with eachnanolayer being generated in a single cycle of the ALD process. Both thecombined thickness of the CVD layer 220 and the ALD layer 230 and therelative thicknesses of these layers 220 and 230 may vary depending onthe material used and the desired capacitance of the capacitor 200. Inone embodiment, the combined thickness of the CVD layer 220 and the ALDlayer 230, referred to collectively as an electrically conductivecoating (225 in FIG. 9B), may be on the order of about 50-500 Å, e.g.,about 150-250 Å. In certain embodiments of the invention, the ALD layer230 has a thickness of no greater than 50 Å, with the balance of theelectrically conductive coating 225 comprising the CVD layer 220.

The ALD layer 230 may be formed of an electrically conductive materialhaving a primary species that is different from a primary species of theelectrically conductive material of the CVD layer 220. In manyembodiments of the present invention, though, the ALD layer 230 and theCVD layer 220 comprise the same primary species (e.g., TiN). As notedabove, though, the CVD layer 220 likely will have a higher impuritycontent, (e.g., TiC or chlorine) than will the ALD layer 230. In oneparticular embodiment, the precursors used to deposit the CVD layer 220are the same precursors used to deposit the ALD layer 230. In otherembodiments wherein the CVD layer 220 and the ALD layer 230 generallycomprise the same primary species, the CVD layer may be formed using oneprecursor or a pair of precursors and the ALD layer 230 may be formedusing a different precursor or pair of precursors.

The electrically conductive coating 225 shown in FIGS. 9A-B comprises asingle CVD layer 220 and a single ALD layer 230. In other embodiments,however, the electrically conductive coating 225 may comprise three ormore layers. As suggested in FIG. 9C, for example, this electricallyconductive coating 225 may comprise an initial ALD layer 230 a depositeddirectly atop the roughened surface 212 of the HSG silicon, a CVD layer220 may be deposited on that initial ALD layer 230 a, and an outer ALDlayer 230 b may be deposited on the irregular surface 222 of the CVDlayer 220. In another embodiment, illustrated in FIG. 9D, theelectrically conductive coating comprises an ALD layer 231 deposited onthe surface 212 of the HSG silicon and a CVD layer 220 on the ALD layer,with the dielectric layer (layer 240 in FIG. 10) deposited on the CVDlayer 220. For reasons noted below, the dielectric layer in selectembodiments of the invention is deposited on or is otherwise in directcontact with a layer deposited via ALD, e.g., ALD layer 230.

In another exemplary embodiment, the electrically conductive layer 225atop the HSG silicon layer 210 comprises a first CVD-deposited layer, anALD-deposited layer atop the first CVD-deposited layer, a secondCVD-deposited layer atop the first ALD-deposited layer, and a secondALD-deposited layer deposited atop the second CVD-deposited layer. Inother embodiments, the electrically conductive layer 225 comprises fiveor more layers, with the layers alternating between CVD-deposited layersand ALD-deposited layers. In still other embodiments, the HSG siliconlayer 210 may be omitted and the electrically conductive layer 225 maybe deposited directly on the surface S of the workpiece W shown in FIG.6. In such an embodiment, the electrically conductive layer 225 willform the entirety of the bottom electrode of the capacitor 200 of FIG.12. Such an electrically conductive layer may comprise three or morealternating ALD-deposited and CVD-deposited layers.

The outer surface 232 of the ALD layer 230, i.e., the surface that isspaced away from the irregular surface 222 of the CVD layer 220, may berelatively smooth. As suggested in FIGS. 9A-B, this surface 232 likelywill not be perfectly flat. On a localized scale, though, the ALD layerwill have a surface roughness that is less than the surface roughness ofthe irregular surface 222 of the CVD layer 220. This smooth surface 232is anticipated to provide a more effective electrical contact betweenthe electrically conductive coating and the subsequently-depositeddielectric layer 240, discussed below.

FIG. 10 schematically illustrates the workpiece W of FIG. 9A afterdeposition of a dielectric layer 240. The HSG silicon layer 210, the CVDlayer 220, and the ALD layer 230 shown in FIG. 9A extend across much orall of the surface of the workpiece W. In one embodiment, the dielectriclayer 240 is deposited on the structure and all four of the layers 210,220, 230, and 240 may cover much if not all of the surface of theworkpiece W. In the embodiment shown in FIG. 10, though, the layersillustrated in FIG. 9A have been patterned to remove excess material,leaving the surface of the opening 206 and, in one embodiment, aperipheral margin of the opening 206 covered. This may be accomplishedusing conventional photolithographic and selective etching techniques.

A wide variety of dielectric materials suitable for use as thedielectric layer 240 are well known in the art of microelectroniccapacitors. As noted in the background section above, the capacitance ofa capacitor can be increased by increasing the dielectric constant ofthe dielectric material and/or reducing the thickness of the dielectricmaterial. Although conventional silica (SiO₂) or silicon nitride (Si₃N₄)may be employed, materials with higher dielectric constants—including,for example, alumina (Al₂O₃), tantala (Ta₂O₅), barium strontium titanate(BST), strontium titanate (ST), barium titanate (BT), lead zirconiumtitanate (PZT), and strontium bismuth titanate (SBT)—may yield acapacitor 200 with a higher capacitance. In one specific example, thedielectric layer 240 comprises alumina. The dielectric layer may bedeposited in any desired fashion, including CVD, ALD, or sputtering.

FIG. 11 schematically illustrates the workpiece W of FIG. 10 after asecond electrode 250 has been deposited on the dielectric layer 240.This second electrode 250 may be formed in any suitable manner. In oneparticular embodiment, the electrode 250 is formed via CVD. The materialof the electrode 250 may be any electrically conductive material that iscompatible with the dielectric layer 240 and the other components of theworkpiece W. In one particular embodiment, the electrode 250 comprisesthe same primary species as the primary species of the CVD layer 220and/or the ALD layer 230. For example, if the CVD layer 220 and the ALDlayer 230 comprise TiN, the electrode 250 may also comprise TiN. In oneparticular embodiment, the electrode 250 is formed using the sameprecursors and the same basic deposition process as those used todeposit the CVD layer 220 and/or the ALD layer 230.

FIG. 12 illustrates the finished capacitor 200. In forming the finishedcapacitor 200, the surface of the workpiece W shown in FIG. 11 may bepatterned using conventional photolithographic and etching techniques.

Methods in accordance with the present invention may be employed tocreate capacitors having a variety of different structures. For example,FIG. 13 illustrates a microelectronic capacitor 200 a in accordance withan alternative embodiment of the invention. Many of the elements of FIG.12 are shown in FIG. 13, and like reference numbers are used in FIGS. 12and 13 to indicate like elements. One difference between the electrodes200 and 200 a is the interface between the electrode 250 and thedielectric layer 240. In the capacitor 200, the electrode 250 maycomprise a bulk layer of material formed, e.g., by a continuous CVDprocess. The capacitor 200 a of FIG. 13 instead employs a second ALDlayer 270 on the outer surface of the dielectric layer 240, i.e., thesurface of the dielectric layer 240 oriented away from the first ALDlayer 230. This second ALD layer 270 may be deposited in much the samefashion as the first ALD layer 230. In select embodiments, the ALD layer270 may have a thickness of no greater than about 50 Å. Because of thehighly conformal nature of ALD coatings, the addition of such a secondALD layer 270 is expected to improve the electrical interface betweenthe dielectric 240 and the outer electrode 250.

FIG. 14 schematically illustrates a capacitor 200 b in accordance withanother embodiment of the invention. Like reference numbers are used inFIGS. 13 and 14 to indicate like elements. One difference between thecapacitors 200 a and 200 b is that the capacitor 200 b of FIG. 14 omitsthe first dielectric layer 230 employed in the capacitor 200 a of FIG.13. Instead, a single ALD layer 270 is disposed between the dielectriclayer 240 and the rest of the top electrode 250.

Further variations of these embodiments are also envisioned. Forexample, the majority of the thickness of the electrode 250 in each ofthe illustrated embodiments comprises a single bulk layer. In otherembodiments of the invention, the electrode 250 may be formed as analternating series of ALD-deposited and CVD-deposited layers.

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense as opposed to anexclusive or exhaustive sense, i.e., in a sense of “including, but notlimited to.” Words using the singular or plural number also include theplural or singular number, respectively. Use of the word “or” in theclaims in reference to a list of items is intended to cover a) any ofthe items in the list, b) all of the items in the list, and c) anycombination of the items in the list.

The above-detailed descriptions of embodiments of the invention are notintended to be exhaustive or to limit the invention to the precise formdisclosed above. Specific embodiments of, and examples for, theinvention are described above for illustrative purposes, but variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize. For example,whereas steps are presented in a given order, alternative embodimentsmay perform steps in a different order. The various embodimentsdescribed herein can be combined to provide further embodiments.

In general, the terms used in the following claims should not beconstrued to limit the invention to the specific embodiments disclosedin the specification, unless the above-detailed description explicitlydefines such terms. While certain aspects of the invention are presentedbelow in certain claim forms, the inventors contemplate the variousaspects of the invention in any number of claim forms. Accordingly, theinventors reserve the right to add additional claims after filing theapplication to pursue such additional claim forms for other aspects ofthe invention.

1. A microfeature workpiece processing system comprising: an enclosuredefining a process chamber adapted to receive a microfeature workpiece;a gas supply adapted to selectively deliver a first gaseous precursor, asecond gaseous precursor, and a third gaseous precursor to the processchamber; and a programmable controller operatively coupled to the gassupply, the controller being programmed to: contemporaneously introducethe first gaseous precursor and the second gaseous precursor from thegas supply to the process chamber to deposit a first electricallyconductive layer on a surface of the microfeature workpiece; terminateintroduction of at least one of the first and second gaseous precursors;alternately introduce a quantity of the first gaseous precursor and aquantity of the second gaseous precursor from the gas supply to theprocess chamber to form a second electrically conductive layer at alocation spaced outwardly from the surface of the microfeatureworkpiece, the second electrically conductive layer having a thicknessof no greater than 50A; and thereafter, introduce the third gaseousprecursor to the process chamber to form a dielectric layer on thesecond electrically conductive layer.
 2. The microfeature workpieceprocessing system of claim 1 wherein the gas supply is further adaptedto deliver a purge gas and the controller is further programmed to purgethe process chamber with the purge gas after introducing the quantity ofthe first gaseous precursor and before introducing the quantity of thesecond gaseous precursor.
 3. The microfeature workpiece processingsystem of claim 1 wherein the first gaseous precursor comprises titaniumand the second gaseous precursor comprises nitrogen.